Overview
Component-level semiconductor life cycle inventory data is hard to come by. The major LCA databases either license at industrial-software prices or aggregate to the chip level without exposing the underlying process flow. That makes it difficult to compare across scenarios or trace where a number actually came from.
REEL LCI fills that gap with a public-data-only semiconductor inventory. Each wafer node is modeled as a complete process flow — typically 1000+ unit operations across 50–80 mask layers — with energy, water, gas, chemical, emission, and waste inventories tracked at every step. Every number traces back to a documented public source: equipment-vendor specs, peer-reviewed papers, corporate sustainability reports, or government and industry publications.
The dataset is intended for Scope 3 reporters building product carbon footprints, academic researchers comparing fab-level intensities, and hyperscalers tracing the embodied impact of their hardware procurement back to silicon manufacturing.
What's covered
The semiconductor branch of REEL LCI covers wafer fabrication, integrated-circuit assembly, and package substrates:
- Logic wafers (14 models): 3nm FinFET, 5nm, 7nm, 10nm, 14nm, 22nm, 28nm, 40nm, 65nm, 90nm, 130nm, 180nm planar CMOS, plus BCD analog at 180nm and 20nm logic.
- Memory wafers (8 models): Modern DRAM and NAND wafer flows including 3D NAND layer scaling and HBM die. (See the Memory LCI page for details.)
- Specialty wafers (12 models): Power semiconductor wafers (SiC, GaN), MEMS, image sensor, and other process-differentiated flows.
- Logic ICs (38 models): CPU, GPU, ASIC, and accelerator die at the chip level — combining wafer + die-allocation + yield to per-die inventories.
- IC substrates (2 models): Build-up substrates used under FCBGA and 2.5D packages. (Limited coverage — see the Advanced Packaging LCI page for the packaging side.)
Where multiple scenarios matter — different yield assumptions, region-specific electricity grids, alternative gas-recovery scenarios — REEL publishes them as separate dataset variants. Practitioners select the variant matching their case; the underlying parameters are fixed at publication time, not user-tunable in the consumed dataset.
Methodology
REEL LCI uses a bottom-up "virtual fab" approach. Each process step (lithography exposure, plasma etch, ALD deposition, CMP, wet clean, etc.) is modeled as an independent unit process — equipment power × throughput, gas flows × duration, chemistry consumption × wafer count, with mass-balance closure on inputs and outputs. A wafer model is then a sequence of those steps with explicit pass counts and yields per layer. Support flows (HVAC, ultrapure water systems, abatement, gas delivery, wastewater treatment) are allocated across production volume.
Internally, the modeling engine treats each process flow as code: changing a deposition chemistry, a yield assumption, or a regional electricity grid regenerates the full inventory automatically. That's how REEL can publish multiple node and scenario variants as separate datasets without manually re-authoring each one. Every step references its source — process-flow extraction notes, vendor datasheets, journal papers, sustainability-report disclosures — and uncertainty ranges (min/typical/max) propagate through the calculation. The full methodology, including the data-quality framework and the pedigree-matrix DQI scoring, is documented in the REEL LCI Methodology Report v0.1 (PDF).
Related insights
- The Gas Recovery Inversion — why the abatement scenario can swing direct gas emissions by 2–3x at the same node.
- The Spend-Based GPU Gap — how spend-based emission factors overestimate GPU manufacturing emissions by ~45x compared with primary LCA data.
- The Chiplet Tradeoff — why splitting designs into chiplets shifts carbon from the die to the package.
- The Packaging Crossover — at advanced nodes, the package can cost nearly as much carbon as the chip itself.
Frequently asked questions
REEL LCI covers logic wafers from 3nm FinFET down to 180nm planar CMOS, including 3, 5, 7, 10, 14, 22, 28, 40, 65, 90, 130, and 180nm nodes. The dataset also covers BCD analog, specialty processes, and memory wafers (DRAM, NAND, HBM die). Each node is modeled as a complete process flow — typically 1000+ unit operations across 50–80 mask layers — with energy, water, material, gas, and emission inventories per wafer.
Each wafer model assumes a node-appropriate gas recovery scenario: no recovery for 65nm and 28nm, moderate recovery for 7nm, and best-practice point-of-use abatement for 3nm and 5nm. Fluorinated gases (SF6, CF4, NF3, C4F8, C4F6) are tracked individually with destruction-removal-efficiency assumptions documented per process step. Residual emissions are reported as elementary flows with ecoinvent-compatible naming.
Default datasets assume Taiwan for advanced logic nodes (3–14nm), reflecting the actual concentration of FinFET capacity. Mature nodes (28nm and older) use a generic high-volume manufacturing assumption. Electricity grid mix is the single largest driver of characterized impacts, so users should connect the dataset's electricity input to a region-appropriate grid in their own LCA tool — REEL's published datasets are static, so additional regional variants are added on the REEL side as separate datasets when there's demand.
The methodology is informed by ISO 14040/14044 guidance for life cycle assessment. Elementary flows are mapped to ecoinvent nomenclature for interoperability; emissions use standard compartment classifications. As cradle-to-gate unit processes, the wafer datasets must be paired with a background database (ecoinvent or similar) for upstream materials and electricity, and an LCIA method appropriate to the supply chain. Uncertainty ranges (min/typical/max) are provided to support scenario analysis.