At 3nm with advanced packaging, the package costs nearly as much carbon as the chip itself.
This is one of the findings that kept surprising me while developing the REEL LCI database.
At mature nodes — 180nm, 65nm — wafer fabrication dominates the embodied carbon footprint of an IC. The package (a simple QFN or SOIC) contributes maybe 10–15%. It's almost a rounding error. This matches intuition: the semiconductor fab is the expensive, energy-intensive part.
But as you move to advanced nodes, packaging complexity grows faster than wafer fab complexity. At mature nodes, the package is a commodity — a simple QFN or wire-bond FBGA. At 3nm, it's a second semiconductor process: flip-chip bumping, multi-layer organic substrates with 15+ redistribution layers, 2.5D silicon interposers (CoWoS), through-silicon vias for HBM integration. The packaging step goes from stamping an envelope to building a skyscraper.
The result: for a 3nm logic IC in a CoWoS-S package (think GPU or AI accelerator), the REEL LCI models show packaging contributing roughly 40–45% of the total component-level embodied carbon. For HBM memory stacks, it's even more dramatic — packaging can exceed 70% of the total footprint.
This has real implications for how we think about semiconductor sustainability:
- Packaging technology choice matters as much as process node choice for environmental impact
- The "chiplet" and "heterogeneous integration" trends that save design cost are adding packaging carbon
- Advanced packaging fabs are becoming just as environmentally significant as wafer fabs
The semiconductor industry's environmental conversation is still mostly about wafer fabs. The packaging story is catching up, and fast.
