The package's absolute burden climbs steeply as you move into advanced packaging. The die climbs faster. So the package's share of an integrated circuit goes down, not up, as the node advances.
I went looking for the crossover point where packaging overtakes the die, and in the modelled component set it isn't there. The figures below are screening-level GWP100 results (IPCC 2021) calculated from the inventories in REEL LCI v1.0, released 21 August 2026.
The node series
Take four logic ICs that differ mainly in node and package, and read the package share of the component total:
- 14nm FinFET in a flip-chip BGA: package 1.28 kg CO2e of a 2.74 kg total, 46.8%
- 7nm EUV in the same flip-chip BGA: 1.30 kg of 3.54 kg, 36.8%
- 5nm FinFET in the same flip-chip BGA: 1.30 kg of 4.36 kg, 29.9%
- 3nm GAA in a CoWoS 2.5D package: 11.33 kg of 46.20 kg, 24.5%
The package is not getting cheaper. Between the 5nm part and the 3nm part it goes from 1.30 kg to 11.33 kg, because a 2.5D silicon interposer is a wafer-level process in its own right. Measured on its own, one CoWoS 2.5D package carries about 8.92 kg CO2e against about 0.105 kg for a wire-bond fine-pitch BGA, roughly 85 times as much. But over the same step the die goes from 3.05 kg to 34.87 kg. Both terms grow; the die term grows faster, and the ratio moves the wrong way for a crossover.
Memory stacking behaves the same way. For an HBM3 16GB 8-Hi stack, the TSV stacking operation accounts for 2.02 kg CO2e of a 13.52 kg total, or 15.0%. The eight DRAM core dies and the base logic die carry the other 85%. Stacking is a demanding process, and it is still small next to the silicon it is stacking.
Where packaging does dominate
The largest package shares in the set are not at the leading edge. They are at mature nodes, where the die is tiny and the package is not:
- 130nm logic buffer in a TSSOP: package 0.0611 kg of a 0.0694 kg total, 88.1%
- 180nm op-amp in an SOIC-8: 0.0125 kg of 0.0394 kg, 31.6%
- 65nm MCU in an LQFP-64: 0.0243 kg of 0.1273 kg, 19.1%
- 180nm analog IC in an SOP-8: 0.0125 kg of 0.0664 kg, 18.8%
- 180nm PMIC in a QFN 4x4: 0.0127 kg of 0.0993 kg, 12.8%
Those last four are all mature-node parts, and their package shares run from 12.8% to 31.6%. The 130nm logic buffer sits at 88.1% because each part draws only about one forty-five-thousandth of a wafer, while the package around it is not scaled down to match. Nothing about "mature node" predicts the answer on its own.
What this means in practice
A fixed rule of thumb, packaging is X% of the component, fails in both directions here. Assume 40% at the leading edge and you overstate the package on a 3nm CoWoS part by about a factor of two while understating the die. Assume 10–15% at mature nodes and you are close for a QFN PMIC and badly wrong for a small die in an SOIC or a TSSOP.
Three practical consequences:
- Spend data effort where the mass of the result sits. For advanced logic and for HBM, that is still the wafer: die area, node, and fab electricity mix move the answer far more than the package model does. For small mature-node parts, the package model is the sensitive term.
- Per-package datasets matter more than a packaging factor. The same flip-chip BGA appears at 1.28 to 1.30 kg CO2e across three nodes, so the package is close to a fixed cost per part while the die varies by a factor of two. A model that scales packaging as a percentage of the die will get that backwards.
- Do not treat advanced packaging as negligible in absolute terms. An 85-fold step from wire bond to a 2.5D interposer is real, and in a product with many packaged components it is a large absolute number even when each package is a minority share of its own component.
These are screening results from inventory data, not a full impact assessment, and they carry the uncertainty of the underlying models: die area assumptions, yields, and regional electricity all move them. The direction, though, is consistent across every logic and memory component modelled: at the leading edge the die is still the larger term, and it is pulling away.
