Overview
Memory has become a disproportionate share of embodied carbon in AI hardware. HBM stacks are packaged beside the compute die on current AI accelerators, and high-density NAND fills modern storage. Yet published, component-level memory life cycle inventory data at the resolution practitioners need – by generation, by stack height, by NAND layer count – is hard to find.
REEL LCI provides 39 memory-wafer datasets and 31 memory-component datasets combining wafer fabrication with packaging into per-die, per-device, and per-capacity inventories. Coverage includes current DRAM generations, LPDDR, GDDR7, 3D NAND from 128 to 321 layers, HBM3, HBM3E, HBM4, and HBF, with documented sources and uncertainty ranges.
The dataset is intended for AI hardware vendors, hyperscalers, storage OEMs, and Scope 3 reporters needing memory inventories that distinguish standard DRAM from the very different impact profile of HBM and high-layer NAND.
What's covered
The memory branch of REEL LCI covers wafer fabrication and finished components:
- Memory wafers (39 datasets): DRAM 10nm and 1α/1β/1γ, GDDR7, and 3D NAND from 128 to 321 layers, including supported operating and conventional-versus-cryogenic etch scenarios.
- DRAM components: DDR4, DDR5, LPDDR, GDDR – packaged DRAM die in standard memory packages.
- NAND components: TLC and QLC 3D NAND across multiple density tiers and layer counts.
- HBM and HBF: HBM3, HBM3E, and HBM4 in 8-, 12-, and 16-high configurations where supported, plus HBF, with TSV bonding, base die, stack-yield compounding, and HBM4 ramp/mature scenarios.
Stack heights (4-high vs 8-high vs 12-high HBM), 3D NAND layer counts, and packaging generations are published as separate dataset variants. Practitioners pick the variant matching their specific component.
Browse the documentation for every memory dataset – system boundary, the source or derivation recorded for each flow, exclusions and data quality, dataset by dataset.
Methodology
Memory components combine a wafer model (using the same bottom-up process-flow approach as the broader semiconductor dataset) with a packaging model (wire-bond for standard DRAM/NAND, TSV stacking for HBM). Yields compound across the assembly steps. For HBM specifically, each die-to-die bond carries an assumed yield, and the overall stack yield compounds across the stack height. That means an 8-high HBM stack has meaningfully different per-Gb impacts than two 4-high stacks of the same total density.
For 3D NAND, the wafer-level flow scales the number of deposition cycles, etch passes, and lithography exposures with the layer count, capturing the super-linear relationship between layer count and per-wafer impact. Per-Gb inventories are then a function of die size, layer count, and yield. The full methodology is documented in the REEL LCI Methodology Report v1.0 (PDF).
Related insights
- HBM's Footprint Is a Die-Area Story – the full die-vs-packaging analysis for standard DRAM vs. HBM3.
- The Package Grows, the Die Grows Faster – advanced packages carry far more embodied carbon than wire-bond ones, yet the die grows faster than the package.
- The Packaging Crossover That Isn't – the package's burden climbs with advanced packaging, but the die's climbs faster, so packaging's share of an IC falls at advanced nodes.
- The Spend-Based GPU Gap – why component-level memory inventories matter when accounting for AI hardware in Scope 3.
Frequently asked questions
REEL LCI covers 39 memory-wafer datasets and 31 memory-component datasets. Coverage spans current DRAM generations, LPDDR, GDDR7, 3D NAND from 128 to 321 layers, HBM3, HBM3E, HBM4, and HBF, including supported operating, production-maturity, and conventional-versus-cryogenic NAND scenarios.
A standard DRAM chip is a DRAM die in a wire-bond package. An HBM stack is several DRAM dies and a base logic die bonded vertically with through-silicon vias. REEL LCI models the DRAM wafer, the TSV stacking and the packaging steps as their own datasets, with stack yield compounding across the stack height and per-Gb scaling across stack heights. The figures for how the footprint divides between the wafer and the stacking are in the insight HBM's Footprint Is a Die-Area Story.
3D NAND scales the active storage with the number of vertical layers, but adding layers also adds processing complexity: more deposition cycles, deeper etches, and more challenging lithography for the staircase contacts. The dataset captures this super-linear relationship between layer count and per-wafer energy/chemistry, which translates into a non-linear per-Gb impact curve as layer counts increase.
Default datasets assume South Korea for DRAM and HBM (Samsung, SK Hynix), South Korea or Japan for NAND (also Samsung, SK Hynix, Kioxia), and Taiwan or US for any logic-side controllers. Electricity grid mix and water/wastewater infrastructure all reflect those defaults. Practitioners should adjust the electricity input to match their actual supplier when known.