Overview
Memory has become a disproportionate share of embodied carbon in AI hardware. An HBM3 stack on a flagship GPU contributes more carbon than the GPU compute die underneath it, and high-density NAND in modern storage is similarly dense in embodied impact per gigabyte. Yet public, component-level memory life cycle inventory data at the resolution practitioners need — by generation, by stack height, by NAND layer count — is hard to find.
REEL LCI provides 8 memory wafer flows and 19 memory component models combining wafer fabrication with packaging into per-die and per-Gb inventories. DRAM (DDR4, DDR5, LPDDR), NAND (TLC, QLC, 3D NAND across multiple layer counts), and HBM (with explicit stack-yield compounding) are all covered with documented sources and uncertainty ranges.
The dataset is intended for AI hardware vendors, hyperscalers, storage OEMs, and Scope 3 reporters needing memory inventories that distinguish standard DRAM from the very different impact profile of HBM and high-layer NAND.
What's covered
The memory branch of REEL LCI covers wafer fabrication and finished components:
- Memory wafers (8 models): DRAM die at multiple generations, planar and 3D NAND at multiple layer counts, HBM core die.
- DRAM components: DDR4, DDR5, LPDDR, GDDR — packaged DRAM die in standard memory packages.
- NAND components: TLC and QLC 3D NAND across multiple density tiers and layer counts.
- HBM stacks: HBM2, HBM3, HBM3E — multi-die stacks with TSV bonding, base die, and stack-yield compounding.
Stack heights (4-high vs 8-high vs 12-high HBM), 3D NAND layer counts, and packaging generations are published as separate dataset variants. Practitioners pick the variant matching their specific component.
Methodology
Memory components combine a wafer model (using the same bottom-up process-flow approach as the broader semiconductor dataset) with a packaging model (wire-bond for standard DRAM/NAND, TSV stacking for HBM). Yields compound across the assembly steps — for HBM specifically, each die-to-die bond carries an assumed yield, and the overall stack yield compounds across the stack height. That means an 8-high HBM stack has meaningfully different per-Gb impacts than two 4-high stacks of the same total density.
For 3D NAND, the wafer-level flow scales the number of deposition cycles, etch passes, and lithography exposures with the layer count — capturing the super-linear relationship between layer count and per-wafer impact. Per-Gb inventories are then a function of die size, layer count, and yield. The full methodology is documented in the REEL LCI Methodology Report v0.1 (PDF).
Related insights
- The HBM Footprint Inversion — the full die-vs-packaging analysis for standard DRAM vs. HBM3.
- The Chiplet Tradeoff — the broader pattern: as integration density grows, packaging carries more carbon.
- The Packaging Crossover — at advanced nodes, the package can match the chip itself in embodied impact.
- The Spend-Based GPU Gap — why component-level memory inventories matter when accounting for AI hardware in Scope 3.
Frequently asked questions
REEL LCI covers 8 memory wafer flows (DRAM, NAND, HBM die) and 19 memory components. Coverage spans DDR4, DDR5, LPDDR, GDDR; planar and 3D NAND across multiple layer counts (TLC and QLC); and HBM2/HBM3/HBM3E stacks with explicit TSV bonding and stack-yield compounding.
A standard DRAM chip is roughly 75% wafer / 25% packaging by embodied carbon. An HBM3 memory stack inverts that: roughly 30% wafer / 70% packaging. The reason is the TSV bonding stack — 8 or 12 dies bonded vertically through silicon vias adds substantial packaging burden, while each die itself is smaller. The Memory LCI dataset reflects this with explicit stack-yield compounding and per-Gb scaling across stack heights.
3D NAND scales the active storage with the number of vertical layers, but adding layers also adds processing complexity — more deposition cycles, deeper etches, and more challenging lithography for the staircase contacts. The dataset captures this super-linear relationship between layer count and per-wafer energy/chemistry, which translates into a non-linear per-Gb impact curve as layer counts increase.
Default datasets assume South Korea for DRAM and HBM (Samsung, SK Hynix), South Korea or Japan for NAND (also Samsung, SK Hynix, Kioxia), and Taiwan or US for any logic-side controllers. Electricity grid mix and water/wastewater infrastructure all reflect those defaults — practitioners should adjust the electricity input to match their actual supplier when known.