A 3nm chip can have lower direct process gas emissions than a 7nm chip. The fluorinated gases (SF₆, CF₄, NF₃, C₄F₈) used in plasma etching and chamber cleaning have global warming potentials thousands of times higher than CO₂, so the direct-emissions share is meaningful at advanced nodes.
In the REEL LCI models, direct process gas emissions account for about 8% of total carbon footprint at 7nm – the highest of any logic node we model. At 3nm, they account for about 0.4%. Counting the production of those gases as well, the shares are roughly 9% and 2%.
How is that possible when 3nm uses more process gas in absolute terms?
The answer is gas recovery. The models assume different abatement and gas recovery scenarios by node, reflecting roughly what industry practice looks like at each generation:
- At 65nm and 28nm: no gas recovery. These fabs were built before comprehensive gas management became standard.
- At 7nm: moderate recovery. Transitional generation.
- At 3nm and 5nm: best-practice recovery. The newest fabs invest heavily in point-of-use abatement with high destruction/removal efficiencies.
This isn't really a technology effect. It's a facility investment effect. A 7nm chip made in a fab with best-practice gas recovery would likely have a meaningfully different emissions profile than the baseline model shows.
This matters for anyone interpreting semiconductor carbon data: the abatement scenario can swing direct emissions by roughly a factor of two at the same technology node. If a report gives you a single number for "7nm carbon footprint" without specifying gas recovery assumptions, that number is incomplete.
In the REEL LCI dataset, every model documents its abatement technology, gas recovery scenario, and the parameters that drive the emission calculation. Assumptions that aren't visible can't be questioned.
