Overview
Advanced packaging is increasingly the largest component of embodied carbon in high-performance electronics. As leading-edge designs split monolithic dies into chiplets connected through silicon interposers, fan-out redistribution layers, and through-silicon vias, the "package" stops being a passive lead frame and starts looking like a second semiconductor manufacturing process. The carbon math has shifted accordingly.
REEL LCI provides per-package advanced packaging life cycle inventory data for 39 modeled packages, spanning the full range from conventional wire-bond FBGAs to TSMC CoWoS 2.5D, Intel Foveros and EMIB, fan-out wafer- and panel-level packaging, and HBM TSV stacking. Each package is modeled bottom-up: the underlying processes (interposer fabrication, bonding, underfill, molding, ball attach) are tracked as unit operations with explicit energy, chemistry, and emission inventories.
The dataset is intended for AI hardware vendors, semiconductor IDMs, and Scope 3 reporters tracking the rapidly growing share of embodied carbon attributable to the package rather than the die itself.
What's covered
The advanced packaging branch of REEL LCI covers 39 distinct packages across four broad classes:
- 2.5D and 3D advanced: TSMC CoWoS 2.5D (silicon interposer + chiplet integration), Intel Foveros (3D stacking), Intel EMIB (embedded multi-die interconnect bridge), HBM3 TSV stacking.
- Fan-out: Fan-out wafer-level packaging (FOWLP), fan-out panel-level packaging (FOPLP), embedded wafer-level BGA (eWLB).
- Conventional flip-chip: FCBGA in multiple body sizes (27x27, 32x32, 35x35, 50x50 mm), flip-chip BGA, package-on-package (PoP).
- Wire-bond and lead-frame: QFN (multiple sizes), DFN, DIP, LQFP-64, PLCC, power QFN.
IC substrates used under FCBGA and 2.5D packages are modeled separately; each packaging model documents which substrate dataset it consumes as an input, so the substrate's contribution to the package-level inventory is traceable rather than hidden.
Methodology
Each packaging process step is modeled as a unit process: interposer fabrication uses a wafer-level process flow with TSV etch + fill + RDL plating; chiplet placement and bonding (thermocompression for HBM, mass reflow for FCBGA, hybrid bonding for advanced 3D) carries its own energy and chemistry inventory; underfill, molding, and ball attach contribute the rest. Stack-yield compounding is explicit — bonding-step yield assumptions multiply across the stack height for HBM and 3D constructions.
The package model then assembles those steps with explicit pass counts, area scaling for interposer-based packages, and bond-count scaling for stacked packages. Where multiple chip-attach methods, substrate generations, or underfill chemistries are relevant, REEL publishes them as separate dataset variants — practitioners pick the variant matching their package. The full methodology, including the chiplet-vs-monolithic comparison framework, is documented in the REEL LCI Methodology Report v0.1 (PDF).
Related insights
- The Chiplet Tradeoff — full analysis of the 180x packaging differential and what it means for design economics vs. carbon.
- The HBM Footprint Inversion — why an HBM stack inverts the standard DRAM die-vs-package ratio (75/25 → 30/70).
- The Packaging Crossover — at advanced nodes, the package can match the chip itself in embodied impact.
- The Gas Recovery Inversion — direct gas emissions in the upstream wafer steps that feed advanced packaging.
Frequently asked questions
REEL LCI covers 39 packaging models including TSMC CoWoS 2.5D, Intel Foveros and EMIB, fan-out wafer-level (FOWLP) and panel-level (FOPLP) packaging, embedded wafer-level BGA (eWLB), HBM TSV stacking, and a wide range of conventional packages — FCBGA in multiple sizes (27x27, 32x32, 35x35, 50x50), flip-chip BGA, QFN (multiple sizes), DFN, DIP, LQFP, PLCC, and package-on-package (PoP).
HBM is modeled as the combination of a base die, multiple core dies stacked via through-silicon vias (TSV), and bonding/underfill steps. Stack-yield compounding is explicit — each die-to-die bond carries a yield assumption that compounds across the stack height, which means an 8-high HBM stack has meaningfully different per-Gb impacts than two 4-high stacks. The HBM3 TSV stacking process file documents the bonding energy, underfill chemistry, and TSV via density used.
Chiplet designs split a monolithic die into smaller chiplets connected through advanced packaging — silicon interposers, redistribution layers, through-silicon vias. That connection technology looks a lot like a second semiconductor manufacturing process: lithography, plating, etch, deposition. CoWoS 2.5D packaging carries roughly 180x the carbon footprint of a conventional wire-bond FBGA, so the chiplet yield savings on the die side are partially offset by the packaging carbon required to put the chiplets back together.
Default datasets assume Taiwan for CoWoS and FOWLP (where TSMC dominates capacity), South Korea for HBM stacking (Samsung and SK Hynix), and a generic high-volume manufacturing assumption for conventional packages. Electricity grid mix and facility-level water and abatement infrastructure all reflect those defaults — practitioners should adjust the electricity input to match their actual supplier when known.