A standard DRAM chip: around 75% of its carbon footprint comes from wafer fabrication, 25% from packaging.
An HBM3 memory stack: 30% wafer, 70% packaging.
The ratio doesn't just shift — it inverts.
This is what happens when you take eight to twelve individually fabricated DRAM dies, thin them to 40 micrometers each, drill thousands of through-silicon vias, fill them with copper, and stack them with sub-micron alignment precision. The packaging process becomes the dominant environmental contributor.
The numbers from the REEL LCI models:
- A standard 1a DRAM IC in a wire-bond FBGA package: ~1 kg CO₂e
- An HBM3 8-Hi stack (24 GB): ~50 kg CO₂e
- An HBM3E 12-Hi stack (48 GB): ~80 kg CO₂e
That's a 50–80x increase in embodied carbon from a standard DRAM chip to an HBM stack. Some of that is simply more dies (8–12 vs. 1), but the majority is the TSV stacking, die thinning, and precision assembly that makes HBM possible.
For anyone estimating the embodied carbon of AI servers, GPUs, or data center hardware: HBM is likely the single largest contributor to your component-level footprint. A GPU with six HBM3E 12-Hi stacks could carry nearly 500 kg CO₂e in memory alone.
This isn't well-captured in most available LCI datasets, which tend to model "DRAM" as a monolithic category. The manufacturing process, and its environmental footprint, varies by an order of magnitude depending on the packaging technology.
