Every conversation about AI infrastructure eventually lands on the same constraint: memory. Each HBM3 stack — 24 GB of DRAM — carries roughly 45 kg of embodied CO₂e. A single GPU with six stacks holds nearly 270 kg in memory alone, before the processor.
High Bandwidth Flash (HBF) proposes a different idea: apply HBM-style TSV stacking to 3D NAND flash instead of DRAM. The result sits between HBM and NVMe SSDs — HBM-class bandwidth (1.6 TB/s), flash-class capacity (512 GB per stack), ~10 µs read latency. Essentially memory specialized for inference rather than training.
I built a preliminary HBF Gen 1 model for the REEL LCI database to see what that shift does to embodied carbon.
Per stack, HBF is the most carbon-intensive memory component here — roughly 3.5x an HBM3 8-Hi stack (where it lands against HBM4 is TBD). But per gigabyte of capacity, the picture inverts: HBF comes out about 6x more carbon-efficient per GB.
The packaging mix flips too. HBM is ~70–75% packaging carbon — the through-silicon vias, die thinning, and precision stacking that make it expensive to build. HBF is mostly wafer and die, because each NAND die packs roughly 10x the capacity of a DRAM die, so capacity outruns the higher per-die fabrication burden.
The system-level effect is what makes this interesting. A model too big for HBM today gets sharded across multiple GPUs. Hold it in one device's HBF pool instead, and fewer servers serve the same model — less total embodied carbon at the fleet level, even as each server carries more memory carbon.
A few caveats matter. HBF is pre-commercial, with samples targeted for the second half of 2026, the model still has gaps, and the per-GB comparison flatters HBF — you cannot run latency-critical work on 10 µs flash. These are screening-level estimates from a virtual fab, not a real manufacturer's process.
As the memory hierarchy deepens, counting HBM stacks and multiplying by a single carbon factor stops being enough. The modeling has to follow the architecture.
