Every conversation about AI infrastructure eventually lands on the same constraint: memory. Each HBM3 stack, 16 GB of DRAM, carries about 13.5 kg of embodied CO₂e. A single GPU with six stacks holds about 81 kg in memory alone, before the processor.
High Bandwidth Flash (HBF) proposes a different idea: apply HBM-style TSV stacking to 3D NAND flash instead of DRAM. The result sits between HBM and NVMe SSDs: HBM-class bandwidth (1.5 TB/s), flash-class capacity (512 GiB per stack, about 550 GB), and roughly 10 µs read latency. Essentially memory specialized for inference rather than training.
I built a preliminary HBF Gen 1 model for the REEL LCI database to see what that shift does to embodied carbon. The figures below are screening-level estimates from REEL LCI v1.0, released 21 August 2026.
Per stack, HBF is the most carbon-intensive memory component here, roughly 17x an HBM3 8-Hi stack (where it lands against HBM4 is TBD). But per gigabyte of capacity, the picture inverts: HBF comes out about 1.9x more carbon-efficient per GB.
The reason is not packaging. In both stacks the carbon sits in the wafers: an HBM3 8-Hi stack is about 85% wafer (75% DRAM core dies, 10% base logic die) against 15% TSV stacking, and an HBF stack is about 96% wafer (65% NAND core dies, 31% CMOS peripheral wafer). What separates them is die density. A 256 Gib NAND die carries roughly 16x the bits of a 16 Gb DRAM die, so capacity outruns the fabrication burden per die.
The system-level effect is what makes this interesting. A model too big for HBM today gets sharded across multiple GPUs. Hold it in one device's HBF pool instead, and fewer servers serve the same model: less total embodied carbon at the fleet level, even as each server carries more memory carbon.
A few caveats matter. HBF is pre-commercial, with samples targeted for the second half of 2026, the model still has gaps, and the per-GB comparison flatters HBF, since you cannot run latency-critical work on 10 µs flash. These are screening-level estimates from a virtual fab, not a real manufacturer's process.
As the memory hierarchy deepens, counting HBM stacks and multiplying by a single carbon factor stops being enough. The modeling has to follow the architecture.
